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mt9v124: 1/13-inch vga soc digital image sensor features ? mt9v124_ds rev.c pub. 5/15 en 1 ?semiconductor components industries, llc 2015, 1/13-inch system-on-a-chip (soc) cmos digital image sensor mt9v124 datasheet, rev. c for the latest datasheet, please visit www.onsemi.com features ? superior low-light performance ? ultra-low-power ?vga video at 30fps ? internal master clock generated by on-chip phase locked loop (pll) oscillator ? electronic rolling shutter (ers), progressive scan ? integrated image flow processor (ifp) for single-die camera module ? one-time programmable memory (otpm) ? automatic image correction and enhancement, including four-channel lens shading correction ? image scaling with anti-aliasing ? supports itu-r bt.656 format with odd timing code ? two-wire serial interface providing access to registers and microcontroller memory ? selectable output data format: ycbcr, 565rgb, and raw8+2-bit, bt656 ? high speed serial data output in 12-bit packet ? independently configurable gamma correction ? direct xdma access (reducing serial commands) ? integrated hue rotation 22 applications ? medical tools, device ?biometrics ? industrial application general description on semiconductor's mt9v124 is a 1/13-inch cmos digital image sensor with an active-pixel array of 648h x 488v. it includes sophisticated camera functions such as auto exposure control, auto white balance, black level control, flicker detection and avoidance, and defect correction. it is designed for low light per- formance. it is programmable through a simple two- wire serial interface. the mt9v124 produces extraordi- narily clear, sharp digital pictures that make it the per- fect choice for a wide range of medical and industrial applications. table 1: key parameters parameter typical value optical format 1/13-inch active pixels 648 x 488 = 0.3 mp (vga) pixel size 1.75 ? m color filter array rgb bayer shutter type electronic rolling shutter (ers) input clock range 18 C 44 mhz output lvds 12-bit packet frame rate, full resolution 30 fps responsivity 1.65 v/lux*sec snr max 33.4 db dynamic range 58 db supply voltage analog 2.5C3.1v digital 1.7C1.95v digital i/o 1.7C1.95v or 2.5C3.1v power consumption 55 mw operating temperature (ambient) -t a C30 c to +70 c chief ray angle 24 package options bare die, csp
mt9v124_ds rev.c pub. 5/15 en 2 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor ordering information ordering information table 2: available part numbers part number product description orderable product attribute description MT9V124D00STCK22DC1-200 rgb color die die sales, 200 ? m thickness mt9v124ebkstc-cr csp with 400 ? m coverglass chip tray without protective film
mt9v124_ds rev.c pub. 5/15 en 3 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 register and variable descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 serial low voltage differential signaling (l vds) output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 two-wire serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 one-time programming memory (otpm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 spectral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
mt9v124_ds rev.c pub. 5/15 en 4 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor list of figures list of figures figure 1: mt9v124 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 2: typical configuration (connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 3: 25-ball assignments (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: sensor core block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 5: pixel color pattern detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 7: six pixels in normal and column mirror read out mode (internal data format before serializer).14 figure 8: eight pixels in normal and column skip 2x readout mode (internal data format before serializer)15 figure 9: pixel readout (no skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 10: pixel readout (x_odd_inc = 3, y_odd_inc = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 11: image flow processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 12: color bar test pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: gamma correction curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 14: 0 hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 15: ?22 hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 16: +22 hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 17: bt656 image data with only odd field sav/eav codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 18: lvds typical serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 19: lvds serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 20: single read from random locati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 21: single read from current location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 22: sequential read, start from rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 23: sequential read, start from curre nt location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 24: single write to random location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 25: sequential write, start at rand om location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 26: chief ray angle (cra) vs. image height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 27: quantum efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 28: two-wire serial bus timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 29: power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 30: package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
mt9v124_ds rev.c pub. 5/15 en 5 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor list of tables list of tables table 1: key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 4: status of output signals during reset and standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 5: ycbcr output data ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 6: rgb ordering in default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7: 2-byte bayer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 8: summary of mt9v124 variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 9: lvds packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 10: lvds serial output data timing (for extclk = 22mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 11: extclk input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 12: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 13: operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 14: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 15: operating/standby current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 16: lvds output port dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 17: lvds output port dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 18: two-wire serial interfac e timing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 19: power up signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 20: package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
mt9v124_ds rev.c pub. 5/15 en 6 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description functional description on semiconductor?s mt9v124 is a 1/13-inch vga cmos digital image sensor with an integrated advanced camera system. this camera system features a microcontroller (mcu), a sophisticated image flow processo r (ifp), and a serial port (using lvds signaling). the microcontroller manages all fu nctions of the camera system and sets key operation parameters for the sensor core to optimize the quality of raw image data entering the ifp. the sensor co re consists of an active pixe l array of 648 x 488 pixels with programmable timing and control circuitry. it also includes an analog signal chain with automatic offset correction, programmable gain, and a 10-bit analog-to-digital converter (adc). the entire system-on-a-chip (soc) has an ultra-low power operational mode and a superior low-light performance that is part icularly suitable for medical applications. the mt9v124 features on semiconductor?s breakthrough low-noise cmos imaging technology that achieves near-ccd image qu ality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advan- tages of cmos. architecture overview the mt9v124 combines a vga sensor core with an ifp to form a stand-alone solution for both image acquisition and processing. both the sensor core and the ifp have internal registers that can be controlled by the user. in normal operation, an integrated microcontroller autonomo usly controls most aspects of operation. the processed image data is transmitted to the ex ternal host system through an lvds bus. figure 1 shows the major functional blocks of the mt9v124. figure 1: mt9v124 block diagram
mt9v124_ds rev.c pub. 5/15 en 7 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description sensor core the mt9v124 has a color image sensor with a bayer color filter arrangement and a vga active-pixel array with electronic rolling shu tter (ers). the sensor core readout is 10 bits. the sensor core also supports separate analog and digital gain for all four color channels (r, gr, gb, b). image flow processor (ifp) the advanced ifp features and flexible pr ogrammability of the mt9v124 can enhance and optimize the image sensor performance. built-in optimization algorithms enable the mt9v124 to operate with factory settings as a fully automatic and highly adaptable system-on-a-chip (soc) for most camera systems. these algorithms include shading correction, defect correction, color interpolation, edge detection, color correction, aperture correction, and image formatting with crop- ping and scaling. microcontroller unit (mcu) the mcu communicates with all functional blocks by way of an internal on semicon- ductor proprietary bus interface. the mcu firmware executes the automatic control algorithms for exposure and white balance. system control the mt9v124 has a phase-locked loop (pll) os cillator that can generate the internal sensor clock from the common system clock. the pll adjusts the incoming clock frequency up, allowing the mt9v124 to run at almost any desired resolution and frame rate within the sens or?s capabilities. low-power consumption is a very important requirement for all components of medical devices. the mt9v124 provides power-conservi ng features, including an internal soft standby mode and a hard standby mode. a two-wire serial interface bus enables read and write access to the mt9v124?s internal registers and variables. the internal registers control the sensor core, the color pipeline flow, the output interface, auto white balance (awb) and auto exposure (ae). output interface image data is provided to the host system by a serial lvds interface. the start bit, 8-bit image data, line_valid, frame_valid and stop bit are packetized in a 12-bit packet. the output data format is available in either raw data or processed data. processed data format includes ycbcr, rgb-565, bt656 with odd sav/eav code. it also supports the soc bypass 8+2 data format over the 12-bit packet. system interfaces figure 2 on page 8 shows typical mt9v124 devi ce connections. for low-noise operation, the mt9v124 requires separate power supplie s for analog and digital sections. both power supply rails should be decoupled from ground using capacitors as close as possible to the die. the mt9v124 provides dedicated signals for digital core and i/o power domains that can be at different voltages. the pll and analog circuitry require clean power sources. table 3, ?pin descriptions,? on page 9 provides the signal descriptions for the mt9v124.
mt9v124_ds rev.c pub. 5/15 en 8 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description figure 2: typical configuration (connection) notes: 1. this typical configuration shows only one scenar io out of multiple possibl e variations for this sen- sor. 2. on semiconductor recommends a 1.5k ?? resistor value for the two-wire serial interface r pull - up ; however, greater values may be used for slower transmission speed. 3. all inputs must be configured with v dd _io. 4. on semiconductor recommends that 0.1f and 1f decoupling capacitors for each power supply are mounted as close as possible to the module (l ow-z path). actual values and numbers may vary depending on layout and design considerations, such as capacitor effective series resistance (esr), dielectric, or power supply source impedance. 5. lvds output requires termination resistor (140 ? ) to be placed closely at the sensor side. v aa 4 analog power s data s clk lvds_p standby a gnd i/o 3 power v aa two-wire serial interface serial interface r pull-up 2 active high standby mode extclk external clock in (18C44 mhz) v dd 4 v dd _io v dd _io 3, 4 digital core power v dd v pp gnd, gnd_pll otpm power (optional) lvds_n r t 140
mt9v124_ds rev.c pub. 5/15 en 9 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description signal descriptions figure 3: 25-ball assignments (top view) power-on reset the mt9v124 includes a power-on reset featur e that initiates a reset upon power-up. a soft reset is issued by writing command s through the two-wire serial interface. table 3: pin descriptions mt9v124 sensor signal name module signal name ball number type description extclk extclk e2 input input clock signal. standby stby a2 input controls sensor s standby mode, active high. sclk sclk d4 input two-wire serial interface clock. s data s data e4 i/o two-wire serial interface data. lvds_p lvds_p e1 output lvds positive output. lvds_n lvds_n d2 output lvds negative output. v dd v dd c2, d5 supply digital power (typ 1.8v). v aa , v dd _pll v aa c1 supply analog and pll power (typ 2.8v). v dd _io v dd _io c3 supply i/o power supply (typ 1.8v). d gnd , gnd_io, gnd_pll d gnd b3, b5, d1 supply digital, i/o, and pll ground. a gnd a gnd b1 supply analog ground. v pp v pp a1 supply otpm power dnu dnu a3,a4,a5,b2,b4, c4,c5,d3,e3,e5 1 2 3 4 5 v pp dnu v aa gnd dnu v dd dnu stdby v dd _io dnu dnu a gnd s data dnu dnu extclk lvds_p dnu sclk dnu g nd gnd dnu lvds_n a b c d e v dd
mt9v124_ds rev.c pub. 5/15 en 10 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description standby the mt9v124 supports two different standby modes: ? hard standby mode ? soft standby mode the hard standby mode is invoked by assert ing standby pin. it then disables all the digital logic within the image sensor, and only supports being awoken by de-asserting the standby pin. the soft standby mode is enabled by a single register access, which then disables the sensor core and most of the digital logic. however, the two-wire serial interface is kept alive, which allows the imag e sensor to be awoken via a serial register access. all output signal status during standby are shown in table 4. module id the mt9v124 provides 4 bits of module id th at can be read by the host processor from register 0x001a[15:12]. the module id is programmed through the otpm. table 4: status of output si gnals during reset and standby signal reset post-reset standby lvds_p high-z high-z high-z lvds_n high-z high-z high-z
mt9v124_ds rev.c pub. 5/15 en 11 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description image data output interface the high speed lvds output port on mt9v124 can transmit the sensor image data to the host system over a lengthy differential twisted pair cable. the mt9v124 provides a serial high-speed output port, which is able for driving stan- dard ieee 1596.3-1996 lvds rece iver/deserializers such as the ds92lv1212a lvds deserializer by national semiconductor. image data is provided to the host system by the serial lvds interface. the start bit, 8-bit image data, lv, fv, and stop bit are packetized in a 12-bit packet. the output interface block can select either raw data or processed data. processed data format includes ycbcr, rgb-565, and bt656 with odd sav/eav code. it also supports the soc bypass 8+2 data format over the 12-bit packet. the lvds port is disabled when hard standby or soft standby is asserted.
mt9v124_ds rev.c pub. 5/15 en 12 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description sensor control the sensor core of the mt9v124 is a progress ive-scan sensor that generates a stream of pixel data at a constant frame rate. figure 4 shows a block diagram of the sensor core. it includes the vga active-pixel array. the ti ming and control circuitry sequences through the rows of the array, resetting and then read ing each row in turn. in the time interval between resetting a row and reading that row, the pixels in the row integrate incident light. the exposure is controlled by varying the time interval between reset and readout. once a row has been selected, the data from each column is sequenced through an analog signal chain, including offset corr ection, gain adjustment, and adc. the final stage of sensor core converts the output of the adc into 10-bit data for each pixel in the array. the pixel array contains optically active and light-shielded (dark) pixels. the dark pixels are used to provide data for the offset-correction algorithms (black level control). the sensor core contains a set of control and status registers that can be used to control many aspects of the sensor behavior including the frame size, exposure, and gain setting. these registers are controlled by th e mcu firmware and are also accessible by the host processor through the two-wire serial interface. the output from the sensor core is a bayer pattern; alternate rows are a sequence of either green and red pixels or blue and gree n pixels. the offset and gain stages of the analog signal chain provide per-color control of the pixel data. figure 4: sensor core block diagram sensor core control registers system control 10-bit data out g1/g2 r/b g1/g2 r/b green1/green2 channel red/blue channel vga active-pixel sensor (aps) array analog processing adc digital processing timing and control
mt9v124_ds rev.c pub. 5/15 en 13 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description the sensor core uses a bayer color pattern, as shown in figure 5. the even-numbered rows contain green and red pixels; odd-numbered rows contain blue and green pixels. even-numbered columns contain green and blue pixels; odd-numbered columns contain red and green pixels. figure 5: pixel color pattern detail the mt9v124 sensor core pixel array is shown with pixel (0,0) in the bottom right corner, which reflects the actual layout of the array on the die. figure 6 on page 14 shows the image shown in the sensor during normal operation. when the image is read out of the sensor, it is read one row at a time, with the rows and columns sequenced. column readout direction row readout direction black pixels first clear pixel gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gr b gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r gb r
mt9v124_ds rev.c pub. 5/15 en 14 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description figure 6: imaging a scene the sensor core supports different readout opti ons to modify the image before it is sent to the ifp. the readout can be limited to a spec ific window size of the original pixel array. by changing the readout order, the image can be mirrored in the horizontal direction. the image output size is set by programmi ng row and column start and end address registers. the edge pixels in the 648 x 488 array are present to avoid edge effects and should not be included in the visible window. when the sensor is configured to mirror the image horizontally, the order of pixel readout within a row is reversed, so that read out starts from the last column address and ends at the first column address. figure 7 shows a sequence of 6 pixels being read out with normal readout and reverse readout. this change in sensor core output is corrected by the ifp. figure 7: six pixels in normal and column mirror readout mode (internal data format before serializer) lens pixel (0,0) row readout order column readout order scene sensor (rear view) d out [9:0] line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) reverse readout g2 (9:0) r2 (9:0) r1 (9:0) g1 (9:0) r0 (9:0) g0 (9:0) d out [9:0]
mt9v124_ds rev.c pub. 5/15 en 15 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description figure 8: eight pixels in normal and column sk ip 2x readout mode (internal data format before serializer) figure 9 on page 15 through figure on page 17 show the different skipping modes supported in mt9v124. figure 9: pixel readout (no skipping) d out [9:0] line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) g3 (9:0) r3 (9:0) d out [9:0] line_valid column skip readout g0 (9:0) r0 (9:0) g2 (9:0) r2 (9:0) r2 (9:0) x incrementing y incrementing
mt9v124_ds rev.c pub. 5/15 en 16 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description figure 10: pixel readout (x_odd_inc = 3, y_odd_inc = 1) x incrementing y incrementing
mt9v124_ds rev.c pub. 5/15 en 17 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description image flow processor image control processing in th e mt9v124 is implemented in the ifp hardware logic. the ifp registers can be programmed by the ho st processor. for normal operation, the microcontroller automatically adjusts the operational parameters of the ifp. figure 11 shows the image data processing flow within the ifp. figure 11: image flow processor for normal operation of the mt9v124, streams of raw image data from the sensor core are continuously fed into the color pipeline. the mt9v124 features an automatic color bar test pattern genera tion function to emulate sensor images as shown in figure 12 on page 18. color bar test pattern generation can be selected by programming a register. vga pixel array adc raw data raw 10 digital gain control, shading correction defect correction, nosie reduction, color interpolation, mux ifp color correction aperture correction gamma correction (10-to-8 lookup) statistics engine color kill scaler output formatting yuv to rgb 10/12-bit rgb 8-bit rgb 8-bit yuv rgb to yuv tx fifo lvds output output interface serializer test pattern hue rotate
mt9v124_ds rev.c pub. 5/15 en 18 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description figure 12: color bar test pattern test pattern example reg= 0x8400, 0x15 // seq_cmd reg= 0x8400, 0x16 // seq_cmd reg= 0x8400, 0x17 // seq_cmd reg= 0x8400, 0x18 // seq_cmd reg= 0x8400, 0x19 // seq_cmd
mt9v124_ds rev.c pub. 5/15 en 19 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description image corrections image stream processing starts with multiplica tion of all pixel values by a programmable digital gain. this can be independently set to separate values for each color channel (r, gr, gb, b). independent color channel digital gain can be adjusted with variables. lenses tend to produce images whose bright ness is significantly attenuated near the edges. there are also other factors causing fixed pattern signal gradients in images captured by image sensors. the cumulative result of all these factors is known as image shading. the mt9v124 has an embedded shading correction module that can be programmed to counter the shading effects on each individual r, gb, gr, and b color signal. the ifp performs continuous de fect correction that can mask pixel array defects such as high dark-current (hot) pixels and pixels that are darker or brighter than their neighbors due to photoresponse nonuniformity. the modu le is edge-aware with exposure that is based on configurable thresholds. the thre sholds are changed continuously based on the brightness of the current scene. enabling and disabling noise reduction, and setting thresholds can be defined through variable settings. color interpolation and edge detection in the raw data stream fed by the sensor core to the ifp, each pixel is represented by a 10-bit integer, which can be considered proportional to the pixel?s response to a one- color light stimulus, red, green, or blue, depending on the pixel?s position under the color filter array. initial data processing step s, up to and including the defect correction, preserve the one-color-per-pixel nature of th e data stream, but after the defect correc- tion it must be converted to a three-colors -per-pixel stream appropriate for standard color processing. the conversion is done by an edge-sensitive color interpolation module. the module adds the incomplete color information available for each pixel with information extracted from an appropri ate set of neighboring pixels. the algorithm used to select this set and extract the in formation seeks the best compromise between preserving edges and filtering out high-frequency noise in flat field areas. the edge threshold can be set th rough variable settings. color correction and aperture correction to achieve good color fidelity of the ifp outp ut, interpolated rgb values of all pixels are subjected to color correction. the ifp multiplies each vector of three pixel colors by a 3 x 3 color correction matrix. the color correction matrix can either be programmed by the user or automatically selected by the awb algorithm implemented in the ifp. color correction should ideally produce output colors that are independent of the spectral sensitivity and color crosstalk characteristics of the image sensor. the optimal values of the color correction matrix elements depend on those sensor characteristics. the color correction variables can be adjusted through variable settings. to increase image sharpness, a programmable 2d aperture correction (sharpening filter) is applied to color-corrected image data. the gain and threshold for 2d correction can be defined through variable settings.
mt9v124_ds rev.c pub. 5/15 en 20 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description gamma correction the gamma correction curve (as shown in figure 13) is implemented as a piecewise linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit output. the abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280, 1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096. the mt9v124 ifp includes a block for gamma correction that has the capability to adjust its shape, based on brightness, to enhance the performance under certain lighting conditions. two custom gamma correction tables may be uploaded, one corre- sponding to a brighter lighting condition, the other one corresponding to a darker lighting condition. the final gamma correction table used depends on the brightness of the scene and can take the form of either uplo aded tables or an interpolated version of the two tables. a single (non-adjusting) ta ble for all conditions can also be used. figure 13: gamma correction curve special effects like negative image, sepia, or b/w can be applied to the data stream at this point. these effects can be enabled and selected by registers. to remove high- or low-light color artifacts, a color kill circuit is included. it affects only pixels whose luminance exceeds a certain preprogrammed threshold. the u and v values of those pixels are attenuated proporti onally to the difference between their lumi- nance and the threshold. gamma correction 0 50 100 150 200 250 300 0 1000 2000 3000 4000 input rgb, 12-bit output rgb, 8-bit 0.45
mt9v124_ds rev.c pub. 5/15 en 21 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description image scaling and cropping to ensure that the size of images output by the mt9v124 can be tailored to the needs of all users, the ifp includes a scaler module. when enabled, this module performs resca- ling of incoming images?shrin ks them to selected width and height without reducing the field of view and without discarding any pixel values. the scaler ratios are computed from image output size and the fov. the scaled output must not be greater than 352. output widths greater than this must not use the scaler. by configuring the cropped and output wind ows to various sizes, different zooming levels for 4x, 2x, and 1x can be achieved. th e height and width definitions for the output window must be equal to or smaller than the cropped image. the image cropping and scaler module can be used together to implement a digital zoom. hue rotate the mt9v124 has integrated hue rotate. this feature will help for improving the color image quality and give customers the flexibility for fine color adjustment and special color effects. figure 14: 0 hue reg= 0xa00f, 0x00 // cam_hue_angle
mt9v124_ds rev.c pub. 5/15 en 22 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description figure 15: C22 hue figure 16: +22 hue reg= 0xa00f, 0xea // cam_hue_angle reg= 0xa00f, 0x16 // cam_hue_angle
mt9v124_ds rev.c pub. 5/15 en 23 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description auto exposure the ae algorithm performs automatic adjustments of the image brightness by controlling exposure time, and analog gains of the sensor core as well as digital gains applied to the image. the ae algorithm analyzes image statistics collected by the exposure measurement engine, and then programs the sensor core and color pipeline to achieve the desired exposure. ae uses 4 x 4 exposure statistics windows, which can be scaled in size to cover any portion of the image. the mt9v124 uses average brightness tracking (average y), which uses a constant average tracking algorithm where a target brightness value is compared to a current brightness value, and the gain and integration time are adjusted accordingly to meet the target requirement. the mt9v124 also has a weighted ae algorithm that allows the sensor to be configured to respond to scene illuminance based on each of the weights in the windows. the auto exposure can be configured to respond to scene illuminance based on certain criteria by adjusting gains and integr ation time based on scene brightness. auto white balance the mt9v124 has a built-in awb algorithm de signed to compensate for the effects of changing spectra of the scene illumination on the quality of the color rendition. the algorithm consists of two major parts: a measurement engine performing statistical analysis of the image and a module performing the selection of the optimal color correc- tion matrix, digital, and sensor core analog gains. while default settings of these algo- rithms are adequate in most situations, th e user can reprogram base color correction matrices and place limits on color channel gains. the awb algorithm estimates the dominant co lor temperature of a light source in a scene and adjusts the b/g, r/g gain ratios accordingly to produce an image for srgb display in which grey and white surfaces ar e reproduced faithfully. this usually means that r,g,b are roughly equal for thes e surfaces hence the word ?balance?. the awb algorithm uses statistics collected fr om the last frame to calculate the required b/g and r/g ratios and set the blue and red analog sensor gains and digital soc gains to reproduce the most accurate grey and white surfaces flicker detection and avoidance flicker occurs when the integration time is not an integer multiple of the period of the light intensity. the automatic flicker dete ction module does not compensate for the flicker, but rather avoids it by detecting the flicker frequency and adjusting the integra- tion time. for integration times below the light intensity period (10ms for 50hz environ- ment, 8.33ms for 60hz environment), flicker cannot be avoided. while this fast flickering is marginally detectable by the human eye, it is very noticeable in digital images because the flicker period of the light source is very close to the range of digital images? exposure times. many cmos sensors use a ?rolling shutter? readout mechanism that greatly improves sensor data readout times. this allows pixel data to be read out much sooner than other methods that wait until the entire exposure is complete before reading out the first pixel data. the rolling shutter mechanism exposes a range of pixel rows at a time. this range of exposed pixels starts at the top of the image and then ?rolls? down to the bottom
mt9v124_ds rev.c pub. 5/15 en 24 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description during the exposure period of the frame. as each pixel row completes its exposure, it is ready to be read out. if the light source osci llates (flickers) during this rolling shutter exposure period, the image appears to have alternating light and dark horizontal bands. if the sensor uses the traditional snapshot readout mechanism, in which all pixels are exposed at the same time and then the pixel data is read out, then the image may appear overexposed or underexposed due to light fluctuations from the flickering light source. lights operating on ac electric systems prod uce light flickering at a frequency of 100hz or 120hz, twice the freq uency of the power line. to avoid this flicker effect, the exposure ti mes must be multiples of the light source flicker periods. for example, in a scene lit by 120hz lighting, the available exposure times are 8.33ms, 16.67ms, 25ms, 33.33ms, and so on. (the need for an exposure time less than 8.33ms under artifici al light is extremely rare.) in this case, the ae algorithm must limit the integration time to an integer multiple of the light?s flicker period. by default, the mt9v124 does all of this auto matically, ensuring that all exposure times avoid any noticeable light flicker in the scene. the mt9v124 ae algorithm is always setting exposure times to be integer multipliers of either 100hz or 120hz. the flicker detection module keeps monitoring the incomi ng frames to detect whether the scene's lighting has changed to the other of the two light source frequencies. a 50hz/60hz tung- sten lamp can be used to calibrate the flicker detect settings. output conversion and formatting the yuv data stream can either exit the color pi peline as is or be converted before exit to an alternative yuv or rgb data format. color conversion formulas y'u'v' this conversion is bt 601 scaled to make yuv range from 0 through 255. this setting is recommended for jpeg encoding and is the most popular, although it is not well defined and often misused in various operating systems. (eq 1) (eq 2) (eq 3) there is an option where 128 is not added to u'v'. y'cb'cr' using srgb formulas the mt9v124 implements the srgb standard. this option provides ycbcr coefficients for a correct 4:2:2 transmission. note: 16 < y601< 235; 16 < cb < 240; 16 < cr < 240; and 0 < = rgb < = 255 (eq 4) (eq 5) (eq 6) y ? 0.299 r ? 0.587 g ? 0.114 b ? ? + ? + ? = u ? 0.564 (b ? y ? ? ? 128 + ? = v ? 0.713 (r ? y ? ? ? 128 + ? = y ? (0.2126 r ? 0.7152 g ? 0.0722 b ? ? (219 256) + 16 ? ? ? + ? + ? = cb ? 0.5389 (b ? y ? ? (224 256) + 128 ? ? ? ? = cr ? 0.635 (r ? y ? ? (224 256) + 128 ? ? ? ? =
mt9v124_ds rev.c pub. 5/15 en 25 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description y'u'v' using srgb formulas these are similar to the previous set of formulas, but have yuv spanning a range of 0 through 255. (eq 7) (eq 8) (eq 9) there is an option to disable adding 128 to u'v'. the reverse transform is as follows: (eq 10) (eq 11) (eq 12) uncompressed yuv/rgb data ordering the mt9v124 supports swapping ycbcr mode, as illustrated in table 5. the rgb output data ordering in default mode is shown in table 6. the odd and even bytes are swapped when luma/chroma swap is enabled. r and b channels are bitwise swapped when chroma swap is enabled. uncompressed 10-bit bypass output raw 10-bit bayer data from the sensor core can be output in bypass mode by using d out [7:0] with a special 8 + 2 data format, shown in table 7. table 5: ycbcr output data ordering mode data sequence default (no swap) cb i y i cr i y i+1 swapped crcb cr i y i cb i y i+1 swapped yc y i cb i y i+1 cr i swapped crcb, yc y i cr i y i+1 cb i table 6: rgb ordering in default mode mode (swap disabled) byte d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 565rgb odd r 7 r 6 r 5 r 4 r 3 g 7 g 6 g 5 even g 4 g 3 g 2 b 7 b 6 b 5 b 4 b 3 table 7: 2-byte bayer format byte bits used bit sequence odd bytes 8 data bits d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 even bytes 2 data bits + 6 unused bits 0 0 0 0 0 0 d 1 d 0 y ? 0.2126 r ? 0.7152 g ? 0.0722 b ? 128 + ? + ? + ? = u ? 0.5389 (b ? y ? ) ? 128 0.1146 ? r ' 0.3854 g ' 0.5 b ' 128 + ? + ? ? ? = + ? = v ? 0.635 (r ? y ? ? ? ? 128 0.5 r ' 0.4542 g ' 0.0458 b ' 128 + ? ? ? ? ? = + = r ? y 1.5748 v 128 ? ?? ? + = g ? y 0.1873 (u 128 ? ? ? ? 0.4681 (v 128) ? ? ? = b ? y 1.8556 (u 128) ? ? + =
mt9v124_ds rev.c pub. 5/15 en 26 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor functional description bt656 yuv data can also be output in bt656 format with only odd field sav/eav codes. the bt656 data output will be progressive data an d not interlaced (r0x3c00[5] = 1). figure 17 depicts the data format before the serializer internal to the device, or after the external deserializer. figure 17: bt656 image data with only odd field sav/eav codes "dujwf7jefp %bub <> $c : $s : $c : $s : $c : $s : '' '' % '' $c : $s : '' # 4"7 *n bhf &"7 4"7 *n bhf &"7 )#mbol )#mbol #mboljoh #mboljoh #mboljoh )#mbol
mt9v124_ds rev.c pub. 5/15 en 27 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor register and variable description register and variable description to change internal registers and ram vari ables of mt9v124, use the two-wire serial interface through the external host device. the sequencer is responsible for coordinating all events triggered by the user. the sequencer provides the high-level cont rol of the mt9v124. commands are written to the command variable to start streaming, stop streaming, and to select test pattern modes. command execution is confirmed by reading back the command variable with a value of zero. the sequencer state variable can also be checked for transition to the desired state. all configuration of the sensor (start/stop row/column, mirror, skipping) and the soc (image size, format) and automati c algorithms for ae, awb, low light, are performed when the sequencer is in the stopped state. when the sequencer is in the idle or test pattern state the algorithms and register updates are not performed, allowing the host complete manual control table 8: summary of mt9v124 variables name info monitor variables general information sequencer variables programming control interface fd variables flicker detect ae_track variables auto exposure awb variables auto white balance stat variables statistics low light variables low light cam variables sensor specific settings
mt9v124_ds rev.c pub. 5/15 en 28 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor serial low voltage differential signaling (lvds) output serial low voltage differential signaling (lvds) output the mt9v124 provides a serial high-speed output port which supports all the data formats. mt9v124 is intended to drive st andard ieee 1596.3-1996lvds receiver/deseri- alizers. the internal serializer transforms the parallel data into serial in a 12-bit packet, allowing the data be transported via a leng thy (several meters) twisted pair cable. the lvds output requires a differential termination resistor (rtx_term = 140 ? 1%) that must be provided off-chip and close to the lvds pins. figure 18: lvds typical serial interface lvds data packet format the lvds output is the standard 12-bit pack age with start bit, 10-bit payload and stop bit supported by many off the shelf deserializers. table 9 describes the lvds packet format ; figure 19 shows the lvds data timing. table 9: lvds packet format 12-bit packet data format bit[0] start bit 1 bit[1] pixeldata[0] bit[2] pixeldata[1] bit[3] pixeldata[2] bit[4] pixeldata[3] bit[5] pixeldata[4] bit[6] pixeldata[5] bit[7] pixeldata[6] bit[8] pixeldata[7] bit[9] linevalid (lv) bit[10] framevalid (fv) bit[11] stop bit 0
mt9v124_ds rev.c pub. 5/15 en 29 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor serial low voltage differential signaling (lvds) output figure 19: lvds serial output timing if extclk is greater than 22 mhz, the pll mu st be set to obtain an equivalent internal pixel clock to 22 mhz. the internal pixel clock is multiplied by 12 to achieve the serial- izer output frequency of maximum 264 mhz. table 10: lvds serial output data timing (for extclk = 22mhz) name min typical max unit tdw 3.78 3.78 4.629 ns 1/tdw 216 264 264 mbps table 11: extclk input range name min typical max unit extclk 18 22 44 mhz start(1) d0 d1 d2 d3 d4 d5 d6 d7 lv fv stop(0) tdw internal shift clock lvds serial out
mt9v124_ds rev.c pub. 5/15 en 30 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor two-wire serial interface two-wire serial interface the two-wire serial interface bus enables re ad and write access to control and status registers within the mt9v124. the interface protocol uses a master/slave model in which a master controls one or more slave devices. the mt9v124 always op erates in slave mode. the host (master) generates a clock (sclk) that is an input to the mt9v124 and is used to synchronize transfers. data is transferred between the master and the slave on a bidirectional signal (s data ). protocol data transfers on the two-wire serial interf ace bus are performed by a sequence of low- level protocol elements, as follows: 1. a (repeated) start condition 2. a slave address/data direction byte 3. a 16-bit register address (8-bit addresses are not supported) 4. an (a no) acknowledge bit 5. a 16-bit data transfer (8-bit data tran sfers are supported using xdma byte access) 6. a stop condition the bus is idle when both sclk and s data are high. control of the bus is initiated with a start condition, and the bus is released with a stop condition. only the master can generate the start and stop conditions. a start condition is defined as a high-to-low transition on s data while sclk is high. at the end of a transfer, the master can generate a start condition without previously generating a stop cond ition; this is known as a repe ated start or restart condition. a stop condition is defined as a low-to-high transition on s data while sclk is high. data is transferred serially, 8 bits at a ti me, with the most significant bit (msb) trans- mitted first. each byte of data is followed by an acknowledge bit or a no-acknowledge bit. this data transfer mechanism is used for th e slave address/data direction byte and for message bytes. one data bit is transferred during each sclk clock period. s data can change when sclk is low and must be stable while sclk is high. mt9v124 slave address bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. a ?0? in bit [0] indicates a write, and a ?1? indicates a read. the slave address default is 0x7a. messages message bytes are used for sending mt9v124 internal register addresses and data. the host should always use 16-bit address (two by tes) and 16-bit data to access internal registers. refer to read and write cycles in figure 20 on page 31 through figure 24 on page 33. each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the sclk clock period following the data transfer . the transmitter (which is the master when writing, or the slave when reading) releases s data . the receiver indicates an acknowl- edge bit by driving s data low. for data transfers, s data can change when sclk is low and must be stable while sclk is high.
mt9v124_ds rev.c pub. 5/15 en 31 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor two-wire serial interface the no-acknowledge bit is generated when the receiver does not drive s data low during the sclk clock period following a data transf er. a no-acknowledge bit is used to termi- nate a read sequence. typical operation a typical read or write sequence begins by the master generating a start condition on the bus. after the start condition, the master sends the 8-bit slave address/data direction byte. the last bit indicates whether the requ est is for a read or a write, where a ?0? indicates a write and a ?1? indicates a read. if the address matches the address of the slave device, the slave device acknowledges receipt of the address by generating an acknowledge bit on the bus. if the request was a write, the master then tr ansfers the 16-bit register address to which a write will take place. this transfer take s place as two 8-bit sequences and the slave sends an acknowledge bit after each sequen ce to indicate that the byte has been received. the master will then transfer the 16-bit data, as two 8-bit sequences and the slave sends an acknowledge bit after each sequ ence to indicate that the byte has been received. the master stops writing by generat ing a (re)start or stop condition. if the request was a read, the master sends the 8-bi t write slave address/data direction byte and 16-bit register address, just as in the write request. the master then generates a (re)start condition and the 8-bit read slave address/data direction byte, and clocks out the register data, 8 bits at a time. the mast er generates an acknowledge bit after each 8-bit transfer. the data transfer is stopped when the master sends a no-acknowledge bit. single read from random location figure 20 shows the typical read cycle of the host to mt9v124. the first 2 bytes sent by the host are an internal 16-bit register address. the following 2-byte read cycle sends the contents of the registers to host. figure 20: single read from random location s = start condition p = stop condition sr = restart condition a = acknowledge a = no-acknowledge slave to master master to slave slave address 0 s a reg address[15:8] a reg address[7:0] slave address a a 1 sr read data p previous reg address, n reg address, m m+1 a
mt9v124_ds rev.c pub. 5/15 en 32 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor two-wire serial interface single read from current location figure 21 shows the single read cycle without writing the address. the internal address will use the previous address value written to the register. figure 21: single read from current location sequential read, start from random location this sequence (figure 22) starts in the same way as the single read from random loca- tion (figure 20 on page 31). instead of gener ating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 22: sequential read, start from random location sequential read, start from current location this sequence (figure 23) starts in the same way as the single read from current loca- tion (figure 21). instead of generating a no-a cknowledge bit after the first byte of data has been transferred, the master genera tes an acknowledge bit and continues to perform byte reads until ?l? bytes have been read. figure 23: sequential read, start from current location slave address 1 s a read data [15:8] slave address a 1 s p read data [15:8] p previous reg address, n reg address, n+1 n+2 a a read data [7:0] a read data [7:0] a a read data read data previous reg address, n n+1 n+2 n+l-1 a read data slave address a a 1 read data a s slave address 0 s sr a reg address[15:8] a read data read data a reg address[7:0] a read data slave address previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a 1 a a read data read data m+l-2 m+l-1 m+l a s a read data read data previous reg address, n n+1 n+2 n+l-1 n+l a read data slave address a a 1 read data a s s
mt9v124_ds rev.c pub. 5/15 en 33 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor one-time programming memory (otpm) single write to random location figure 24 shows the typical write cycle from the host to the mt9v124. the first 2 bytes indicate a 16-bit address of the internal registers with most-significant byte first. the following 2 bytes indicate the 16-bit data. figure 24: single write to random location sequential write, start at random location this sequence (figure 25) starts in the same way as the single write to random location (figure 24). instead of generating a no-acknowledge bit after the first byte of data has been transferred, the master generates an acknowledge bit and continues to perform byte writes until ?l? bytes have been writte n. the write is terminated by the master generating a st op condition. figure 25: sequential write, start at random location one-time programming memory (otpm) the mt9v124 has one-time programmable memory (otpm) for supporting defect correction, module id, and other customer-related information. there are 2784 bits of otpm available for features such as lens shading correction, color correction matrix, white balance weight, and user-defined information. the otpm programming requires the data to be first placed in otpm buffer and the presence of vpp. the proper proce- dure and timing must be followed. slave address 0 s a reg address[15:8] a reg address[7:0] a write data p previous reg address, n reg address, m m+1 a a slave address 0 s a reg address[15:8] a write data write data a reg address[7:0] a write data previous reg address, n reg address, m m+1 m+2 m+1 m+3 a a a write data write data m+l-2 m+l-1 m+l a a s
mt9v124_ds rev.c pub. 5/15 en 34 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor spectral characteristics spectral characteristics figure 27: quantum efficiency figure 26: chief ray angle (cra) vs. image height cra vs. image height plot image height cra (%) (mm) (deg) 000 5 0.035 1.23 10 0.070 2.46 15 0.105 3.70 20 0.140 4.94 25 0.175 6.18 30 0.210 7.43 35 0.245 8.67 40 0.280 9.90 45 0.315 11.13 50 0.350 12.36 55 0.385 13.57 60 0.420 14.77 65 0.455 15.97 70 0.490 17.14 75 0.525 18.31 80 0.560 19.45 85 0.595 20.58 90 0.630 21.69 95 0.665 22.77 100 0.700 23.83 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 102030405060708090100110 cra (deg) image height (%) - 0 10 20 30 350 400 450 500 550 600 650 700 750 wavelength (nm) quantum efficiency (%) 50 40
mt9v124_ds rev.c pub. 5/15 en 35 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor electrical specifications electrical specifications caution stresses above those listed in table 12 may cause permanent damage to the device. note: this is a stress rating only, and functional oper ation of the device at these or any other conditions above those indicated in the product specification is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. recommended operating conditions table 12: absolute maximum ratings symbol parameter rating unit min max v dd core digital voltage C0.3 2.4 v v dd _io i/o digital voltage C0.3 4.0 v v aa analog voltage C0.3 4.0 v v aa _pix pixel supply voltage C0.3 4.0 v v pp otpm power supply 8 9.5 v v in input voltage C0.3 vdd_io + 0.3 v t op operating temperature (measure at junction) C30 70 c t stg 1 storage temperature C40 85 c table 13: operating conditions symbol parameter min typ max units v dd core digital voltage 1.7 1.8 1.95 v v dd _io i/o digital voltage 2.5 2.8 3.1 v 1.7 1.8 1.95 v v aa analog voltage 2.5 2.8 3.1 v v aa _pix pixel supply voltage 2.5 2.8 3.1 v v pp otpm power supply 8 8.5 9 v t j operating temperature (at junction) C30 55 70 c
mt9v124_ds rev.c pub. 5/15 en 36 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor electrical specifications table 14: dc electrical characteristics symbol parameter condition min max unit v ih input high voltage 0.7 * v dd _io v dd _io + 0.5 v v il input low voltage C0.3 0.3 * v dd _io v i in input leakage current v in = 0v or v in = v dd _io 10 ? a v oh output high voltage v dd _io = 1.8v, i oh = 2ma 1.7 C v v dd _io = 1.8v, i oh = 4ma 1.6 C v v dd _io = 1.8v, i oh = 8ma 1.4 C v v dd _io = 2.8v, i oh = 2ma 2.7 C v v dd _io = 2.8v, i oh = 4ma 2.6 C v v dd _io = 2.8v, i oh = 8ma 2.5 C v v ol output low voltage v dd _io = 1.8v, i oh = 2ma C 0.1 v v dd _io = 1.8v, i oh = 4ma C 0.2 v v dd _io = 1.8v, i oh = 8ma C 0.4 v v dd _io = 2.8v, i oh = 2ma C 0.1 v v dd _io = 2.8v, i oh = 4ma C 0.2 v v dd _io = 2.8v, i oh = 8ma C 0.4 v table 15: operating/standby current consumption f extclk = 44 mhz; voltages = typ or max; t j = typ or max; excludes v dd _io current symbol parameter condition typ unit i dd digital operating current 9.5 ma i aa analog operating current 7 ma i dd _pll pll supply current 5 ma total supply current 21.5 ma total power consumption 55 mw hard standby total standby current when asserting the standby signal 19 a standby power 44 w soft standby (clock on) total standby current f extclk = 44 mhz, soft standby mode 1.67 ma standby power 3.016 mw soft standby (clock off) total standby current so ft standby mode 19 a standby power 44.2 w
mt9v124_ds rev.c pub. 5/15 en 37 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor electrical specifications table 16: lvds output port dc specifications parameter symbol conditions min typ max units output voltage high v oh 1650 mv output voltage low v ol 850 mv differential output voltage v od 280 360 460 mv output offset voltage v os see text 1000 1192 1400 mv single-ended output resistance ro 150 250 ? output resistance mismatch ? ro 12 % reflection coefficient mismatch ?? 8% differential output mismatch ? v od 6mv offset voltage mismatch ? v os see text 30 mv output short-circuit current i sa , i sb 17 ma output short-circuit current i sab 10 ma standing power-supply current i vddio 8ma table 17: lvds output port dc specifications parameter symbol conditions min typ max units clock signal duty cycle clock 250 mhz; c load = 6pf 48 53 5 differential signal rise time t r c load = 6pf 360 ps differential signal fall time t f c load = 6pf 360 ps propagation delay t p c load = 6pf 2.5 ns differential skew t skew c load = 6pf ??
mt9v124_ds rev.c pub. 5/15 en 38 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor electrical specifications table 18: two-wire serial interface timing data f extclk = 22 mhz; v dd = 1.8v; v dd _io = 1.8v; v aa = 2.8v; v aa _pix = 2.8v; v dd _pll = 2.8v notes: 1. this table is based on i 2 c standard (v2.1 january 2000). philips semiconductor. 2. two-wire control is i 2 c-compatible. 3. all values referred to v ihmin = 0.9 v dd and v ilmax = 0.1v dd levels. sensor exclk = 22 mhz. 4. a device must internally provide a hold time of at least 300 ns for the s data signal to bridge the undefined region of the falling edge of s clk . 5. the maximum t hd;dat has only to be met if the device does not stretch the low period ( t low) of the s clk signal. 6. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. this will automa tically be the case if the device does not stretch the low period of the s clk signal. if such a device does stretch the low period of the s clk signal, it must output the next data bit to the s data line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the s clk line is released. 7. cb = total capacitance of one bus line in pf. parameter symbol standard-mode fast-mode unit min max min max s clk clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - ? s low period of the sclk clock t low 4.7 - 1.3 - ? s high period of the sclk clock t high 4.0 - 0.6 - ? s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - ? s data hold time: t hd;dat 0 4 3.45 5 0 6 0.9 5 ? s data set-up time t su;dat 250 - 100 6 -ns rise time of both s data and s clk signals t r - 1000 20 + 0.1cb 7 300 ns fall time of both s data and s clk signals t f - 300 20 + 0.1cb 7 300 ns set-up time for stop condition t su;sto 4.0 - 0.6 - ? s bus free time between a stop and start condition t buf 4.7 - 1.3 - ? s capacitive load for each bus line cb - 400 - 400 pf serial interface input pin capacitance cin_si - 3.3 - 3.3 pf s data max load capacitance cload_sd - 30 - 30 pf s data pull-up resistor rsd 1.5 4.7 1.5 4.7 k ?
mt9v124_ds rev.c pub. 5/15 en 39 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor electrical specifications figure 28: two-wire serial bus timing parameters sclk s data sclk s data write start ack read start ack t shar t ahsr t sdhr t sdsr read sequence write sequence read address bit 7 read address bit 0 register value bit 7 register value bit 0 write address bit 7 write address bit 0 register value bit 7 register value bit 0 t srts t sclk t sdh t sds t shaw t ahsw stop t stps t stph t srth ack
mt9v124_ds rev.c pub. 5/15 en 40 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor power sequence power sequence powering up the sensor requires the supply rails to be applied in a particular order to ensure sensor start up in a normal operation and prevent undesired condition such as latch up from happening. refer to figure 29 and table 19 for detailed timing require- ment. figure 29: power-up sequence table 19: power up signal timing symbol parameter min typ max unit t1 delay from v dd to v aa and v dd _io 0 - 500 ms t2 extclk activation t1 100 - ms t3 internal por duration 70 - - extclks t4 first i 2 c write 50 - - extclks v aa , v dd _io v dd extclk t 2 t 1 internal por s clk s data t 3 t 4
mt9v124_ds rev.c pub. 5/15 en 41 ?semiconductor components industries, llc, 2015. mt9v124: 1/13-inch vga soc digital image sensor package dimensions package dimensions figure 30: package mechanical drawing table 20: package dimensions parameter symbol nominal min max nominal min max millimeters inches package body dimension x a 2.69355 2.66855 2.71855 0.10605 0.10506 0.10703 package body dimension y b 2.69355 2.66855 2.71855 0.10605 0.10506 0.10703 package height c 0.670 0.615 0.725 0.02638 0.02421 0.02854 cavity height (glass to pixel distance) c4 0.041 0.037 0.045 0.00161 0.00146 0.00177 glass thickness c3 0.400 0.390 0.410 0.01575 0.01535 0.01614 package body thickness c2 0.570 0.535 0.605 0.02244 0.02106 0.02382 ball height c1 0.100 0.070 0.130 0.00394 0.00276 0.00512 ball diameter d 0.200 0.170 0.230 0.00787 0.00669 0.00906 total ball count n 25 ball count x axis n1 5 ball count y axis n2 5 ubm u 0.240 0.230 0.250 0.00945 0.00906 0.00984 pins pitch x axis j1 0.500 0.490 0.510 0.01969 0.01929 0.02008 pins pitch y axis j2 0.500 0.490 0.510 0.01969 0.01929 0.02008 bga ball center to package center offset in x-direction x 0 -0.025 0.025 0 -0.00098 0.00098 bga ball center to package center offset in y-direction y 0 -0.025 0.025 0 -0.00098 0.00098 edge to ball center distance along x axis s1 0.347 0.317 0.377 0.01365 0.01247 0.01483 edge ball center distance along y axis s2 0.347 0.317 0.377 0.01365 0.01247 0.01483 a b c d e 1 23 45 cross-section view(e-e) e e bga center(0,0)= package center pixel center(0.13,0) top view bottom view
on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillcs pr oduct/patent coverage may be accessed at www.onsemi.com/site/pdf/ patent-marking.pdf. scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representat ion or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaim s any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data shee ts and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer a pplication by customers technical experts. scillc does not convey any license under its patent rights nor the rights of others. sc illc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such uninte nded or unauthorized applicatio n, buyer shall indemnify and hol d scillc and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to a ll applicable copyright laws and is not for resale in any manner. mt9v124: 1/13-inch vga soc digital image sensor revision history mt9v124_ds rev.c pub. 5/15 en 43 ?semiconductor components industries, llc, 2015 . a-pix is a trademark of semiconductor components industries, llc (s cillc) or its subsidiaries in the united states and/or other countries. revision history rev. c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/5/15 ? updated to on semiconductor template ? removed confidential marking ? updated ?ordering information? on page 2 rev. b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/17/11 ? updated table 20, ?package dimensions,? on page 41 rev. a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7/26/10 ?initial release

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